In a character and picture image information system such as videotex, teletext and the like, when a character multiplexing of a code system is carried out, it is proposed that the (272, 190) majority-logic decodable code is used to carry out the error correction.
The (272, 190) majority-logic decodable code represents that one data packet is formed of 272 bits, in which 190 bits are assigned to information bits and remaining 82 (=272-190) bits are assigned to error correction parity bits.
However, when the (272, 190) majority-logic decodable code is used, upon decoding, the parity check is carried out by parity check bits of 17 bits, A1 to A17. Thus, the majority logic circuit must identify whether the number of "1" bits in the 17 party check bits, A1 to A17, is less than 10 or not. As a result, the majority logic circuit must comprised logic circuits for all different combinations expressed as .sub.17 C.sub.10 mathematically, or 19448 different combinations, thus a great number of AND circuits and OR circuits being required.
Further, an IC on the market is generally two-input or four-input AND circuits and OR circuits and 17-input AND circuit and OR circuit are not available. Therefore, in practice, the majority logic circuit requires much more AND circuits and OR circuits and this is disadvantageous from a manufacturing cost and size or power consumption standpoint.
In addition, if the number of the AND circuits and the OR circuits used is increased, the processing speed of the majority logic circuit becomes low on the whole and this is not preferable in view of reliability.
For this reason, this invention is to provide a majority logic circuit of a very simple circuit arrangement.